страница 1

НГТУ им. Р.Е. Алексеева

Реферат по английскому языку.

The Intel architecture.


студент группы 07-Р-2

Галанин Иван


Чиркунов К.М.

Нижний Новгород, 2009 год.

The Intel architecture is usually called x86. The generic term x86 refers to the most commercially successful instruction set architecture in the history of personal computing. It derived from the model numbers, ending in "86", of the first few processor generations backward compatible with the original Intel 8086. Since then, many additions and extensions have been added to the x86 instruction set, almost consistently with full backwards compatibility. The architecture has been implemented in processors from Intel, Cyrix, AMD, VIA, and many others.


The x86 architecture first appeared as the Intel 8086 CPU released in 1978, a fully 16-bit design based on the earlier Intel 8085. Although not binary compatible, it was designed to allow assembly language programs written for the 8085 to be mechanically translated into the equivalent 8086 assembly. This made the new processor a tempting migration path for 8085 hardware and software vendors, but - mainly due to a wider data bus - not without significant redesign of system hardware. To address this, Intel introduced the almost identical, but externally 8-bit, 8088 which permitted simpler printed circuit boards, demanded fewer (1-bit wide) DRAM chips, and more easily could be interfaced to already established (i.e. low-cost) 8-bit system and peripheral chips. Among other, non technical factors, this contributed to the fact that IBM built their IBM PC around the 8088, despite a presence of 16-bit microprocessors from Motorola, Zilog, and National Semiconductor. Subsequently, the IBM PC became the dominant personal computer platform and the 8088 and its successors became the dominant CPU architecture for desktop and laptop computers.

In 1982 Intel introduced new i80286 supporting protected mode and a larger address space.

At various times, companies such as IBM, NEC, AMD, TI, STM, Fujitsu, OKI, Siemens, Cyrix, Intersil, C&T, NexGen, and UMC started to design and/or manufacture x86 processors intended for personal computers as well as embedded systems. Such x86 implementations are seldom plain copies but often employ different internal microarchitectures as well as different solutions at the electronic and physical levels. Quite naturally, early compatible chips were 16-bit, while 32-bit designs appeared much later. For the personal computer market, real quantities started to appear around 1990 with i386 and i486 compatible processors, often named similarly to Intel's original chips.

Following the fully pipelined i486, Intel introduced the Pentium brand name (which, unlike numbers, could be trademarked) for their new line of superscalar x86 designs.

The instruction set architecture has twice been extended to a larger word size. In 1985, Intel released the 32-bit 80386 (or i386) which gradually replaced the earlier 16-bit chips in computers (although typically not in embedded systems) during the following years; this extended programming model was originally referred to as the i386 architecture (like its first implementation) but Intel later dubbed it IA-32 when introducing its (unrelated) IA-64 architecture. In 1999-2003, AMD extended this 32-bit architecture to 64 bits and referred to it as x86-64 in early documents and later as AMD64. Intel soon adopted AMD's architectural extensions under the name IA-32e which was later renamed EM64T and finally Intel 64. Among these five names, x86-64 is probably the most commonly used, although Microsoft and Sun Microsystems also use the (perhaps even more vendor-neutral) term x64.


The x86 architecture is a variable instruction length, primarily two-address "CISC" design with emphasis on backward compatibility. The instruction set is not typical CISC however, but basically an extended and orthogonalized version of the simple eight-bit 8080 / 8085-architecture. Words are stored in little-endian order and memory access to unaligned addresses is allowed for supported word sizes. All x86 processors are capable of moving at least 16 bits to or from memory with one MOV instruction, and all x86 processors supporting the SSE instructions and/or x64 instructions support moving 128 bits with one MOVDQU instruction. SSE and x64 were added in 1999 and 2000, respectively. However, supported sizes for integers and memory offsets are 8, 16, 32, or 64 bits depending on architecture generation (newer processors include direct support for smaller integers as well). Addressing offsets and other immediate data may be expressed as 8-bit quantities for the frequently occuring cases or contexts where a -128..127 range is enough. Typical instructions are therefore 2 or 3 bytes in length (although some are much longer, and some are single-byte).

To further conserve encoding space, most registers are expressed in opcodes using three bits, and at most one operand to an instruction can be a memory, but this memory operand may also be the destination, while the other operand, the source, can be either register or immediate. This contributes, among other factors, to a code footprint that rivals eight-bit machines and enables efficient use of instruction cache memory. The relatively small number of general registers (also inherited from the 8085 or 8080) has made register-relative addressing (using small immediate offsets) an important method of accessing operands, especially on the stack. Much work has therefore been invested in making such accesses as fast as register accesses, i.e. a one cycle instruction throughput, in most circumstances.

A dedicated floating point unit (or chip) with 80-bit internal registers, the 8087, was developed for the original 8086; later processors incorporated an extended but backwards compatible version of this functionality on the same chip as the main processor. Modern x86 designs still contain a fast 8087-compatible floating point unit as well as a SIMD-unit where instructions works in parallel on one or two 128-bit words, each containing 2 or 4 floating point numbers (64 or 32 bits wide), or, alternatively, 2,4,8 or 16 integers (each 64,32,16 or 8 bits wide). The wide SIMD registers means that existing x86 processors can load or store up to 128 bits of memory data in a single instruction and also perform bitwise operations (although not integer arithmetics) on full 128-bits quantities in parallel. Planned x86 processors will have 256-bit SIMD operations (including 256-bit memory load and store).

x86 registers

The original Intel 8086 and 8088 have fourteen 16-bit registers. Four of them (AX, BX, CX, DX) are general registers (although each may have an additional purpose; for example only CX can be used as a counter with the loop instruction). Each can be accessed as two separate bytes (thus BX's high byte can be accessed as BH and low byte as BL). Four segment registers (CS, DS, SS and ES) are used to form a memory address. There are two pointer registers. SP points to the bottom of the stack and BP which is used to point at some other place in the stack or the memory(Offset). Two registers (SI and DI) are for array indexing. The FLAGS register contains flags such as carry flag, overflow flag and zero flag. Finally, the instruction pointer (IP) points to the next instruction that will be fetched from memory and then executed.

Starting with the AMD Opteron processor, the x86 in 64-bit long mode (as a subset or remset of x86-64 mode) extended the 32-bit registers in a way similar to what 32-bit protected mode had done before (RAX, RBX, RCX, RDX, RSI, RDI, RBP, RSP, RFLAGS, RIP). However, 8 additional 64-bit general registers (R8, R9, ..., R15) were also introduced. The addressing modes were not dramatically changed from 32-bit mode, except that addressing was extended to 64 bits, physical addressing was now sign extended (so memory always added equally to the top and bottom of memory; note that this does not affect linear or virtual addressing), and other selector details were dramatically reduced. DRAM memory was now signed dynamically.

x86 processors also include various special/miscellaneous registers such as control registers (CR0 through 4), debug registers (DR0 through 3, plus 6 and 7), test registers (TR4 through 7), descriptor registers (GDTR, LDTR, IDTR), and a task register (TR).

Although the main registers are "general-purpose" and can be used for anything, it was envisaged that they be used for the following purposes:

  • AX/EAX/RAX: accumulator

  • BX/EBX/RBX: base

  • CX/ECX/RCX: counter

  • DX/EDX/RDX: data/general

  • SI/ESI/RSI: "source index" for string operations.

  • DI/EDI/RDI: "destination index" for string operations.

  • SP/ESP/RSP: stack pointer for top address of the stack.

  • BP/EBP/RBP: stack base pointer for holding the address of the current stack frame.

  • IP/EIP/RIP: instruction pointer. Holds the current instruction address.

No particular purposes were envisaged for the other 8 registers available only in 64-bit mode.
Operating modes

x86 processors have three operating modes: real mode, protected mode and 64-bit Long mode.

Real mode is an operating mode of 80286 and later x86-compatible CPUs. Real mode is characterized by a 20 bit segmented memory address space (meaning that only 1 MB of memory can be addressed), direct software access to BIOS routines and peripheral hardware, and no concept of memory protection or multitasking at the hardware level. All x86 CPUs in the 80286 series and later start up in real mode at power-on; 80186 CPUs and earlier had only one operational mode, which is equivalent to real mode in later chips.

In order to use more than 64 KB of memory, the segment registers must be used. This created great complications for C compiler implementers who introduced odd pointer modes such as "near", "far" and "huge" to lever the implicit nature of segmented architecture to different degrees, with some pointers containing 16-bit offsets within implied segments and other pointers containing segment addresses and offsets within segments.

In addition to real mode, the Intel 80286 supports protected mode, expanding addressable physical memory to 16 MB and addressable virtual memory to 1 GB, and providing protected memory, which prevents programs from corrupting one another. This is done by using the segment registers only for storing an index to a segment table. There were two such tables, the Global Descriptor Table (GDT) and the Local Descriptor Table (LDT), each holding up to 8192 segment descriptors, each segment giving access to 64 KB of memory. The segment table provided a 24-bit base address, which can be added to the desired offset to create an absolute address. Each segment can be assigned one of four ring levels used for hardware-based computer security.

The Intel 80386 introduced support in protected mode for paging, a mechanism making it possible to use virtual memory.

Paging is used extensively by modern multitasking operating systems. Linux, 386BSD and Windows NT were developed for the 386 because it was the first Intel architecture CPU to support paging and 32-bit segment offsets. The 386 architecture became the basis of all further development in the x86 series.

x86 processors that support protected mode boot into real mode for backward compatibility with the older 8086 class of processors. Upon power-on (aka booting), the processor initializes in real mode, and then begins executing machine code stored in ROM. An operating system boot sequence may place the processor into the Protected mode which enables paging and other features. The instruction set in protected mode is backward compatible with the one used in real mode.

By 2002, it was obvious that the 32-bit address space of the x86 architecture was limiting its performance in applications requiring large data sets. A 32-bit address space would allow the processor to directly address only 4 GB of data, a size surpassed by applications such as video processing and database engines, while using the 64-bit address, one can directly address 16777216 TB (more than 17 billion GB) of data, although most 64-bit architectures don't support access to the full 64-bit address space (AMD64, for example, supports only 48 bits, split into 4 paging levels, from a 64-bit address).

AMD developed the extension of the 32-bit x86 architecture to 64-bit that is currently used in x86 processors, initially calling it x86-64, later renaming it AMD64. The Opteron, Athlon 64, Turion 64, and later Sempron families of processors use this architecture. The success of the AMD64 line of processors coupled with the lukewarm reception of the IA-64 architecture forced Intel to release their own implementation of the AMD64 instruction set. Intel had previously implemented support for AMD64 but opted not to enable it in hopes that AMD would not bring AMD64 to market before Itanium's new IA-64 instruction set was widely adopted. They branded their implementation of AMD64 as EM64T, and later re-branded it Intel 64.

In its literature and product version names, Microsoft and Sun refer to AMD64/Intel 64 collectively as x64 in the Windows and Solaris operating systems respectively. Linux distributions refer to it either as "x86-64", its variant "x86_64", or "amd64". BSD systems use "amd64" while Mac OS X uses "x86_64".

Long mode is mostly an extension of the 32-bit instruction set, but unlike the 16–to–32-bit transition, many instructions were dropped in the 64 bit mode. This does not affect actual binary backward compatibility (which would execute legacy code in other modes that retain support for those instructions), but it changes the way assembler and compilers for new code have to work.

This was the first time that a major upgrade of the x86 architecture was initiated and originated by a manufacturer other than Intel. It was also the first time that Intel accepted technology of this nature from an outside source.


The major extensions of the x86 processor architecture are: MMX, SSE, 3DNow! and Physical Address Extension (PAE).

MMX is a SIMD instruction set designed by Intel, introduced in 1997 for Pentium MMX microprocessors. It developed out of a similar unit first used on the Intel i860. It first appeared in the Pentium MMX. It is supported on most subsequent IA-32 processors by Intel and other vendors. MMX is typically used for video applications.

In 1999, Intel introduced the Streaming SIMD Extensions (SSE) instruction set, following in 2000 with SSE2. The first addition allowed offloading of basic floating-point operations from the x87 stack and the second made MMX almost obsolete and allowed the instructions to be realistically targeted by conventional compilers. Introduced in 2004 along with the Prescott revision of the Pentium 4 processor, SSE3 added specific memory and thread-handling instructions to boost the performance of Intel's Hyper-Threading technology. AMD licensed the SSE3 instruction set and implemented most of the SSE3 instructions for its revision E and later Athlon 64 processors. The Athlon 64 does not support Hyper-Threading and lacks those SSE3 instructions used only for Hyper-Threading.

SSE is suitable for scientific calculations and SSE2 is much more suitable for it than either SSE1 or 3DNow!, which were limited to only single precision. SSE3 does not introduce any additional registers.

In 1997 AMD introduced 3DNow! The introduction of this technology coincided with the rise of 3D entertainment applications and was designed to improve the CPU's vector processing performance of graphic-intensive applications. 3D video game developers and 3D graphics hardware vendors use 3DNow! to enhance their performance on AMD's K6 and Athlon series of processors.

3DNow! was designed to be the natural evolution of MMX from integers to floating point.

By default, physical addresses are 32-bit, however, there exists a page extension mode called Physical Address Extension or PAE, first added in the Intel Pentium Pro, which allows an additional 4 bits of physical addressing. The size of memory in Protected mode is usually limited to 4 GB. Through tricks in the processor's page and segment memory management systems, x86 operating systems may be able to access more than 32-bits of address space, even without the switchover to the 64-bit paradigm. This mode does not change the length of segment offsets or linear addresses; those are still only 32 bits.


x86 – общее название семейства микропроцессоров, как разработанных и выпускаемых компанией Intel, так и совместимых с ними процессоров других производителей (AMD, VIA, Transmeta, WinChip и т. д.). Такое имя закрепилось за семейством этих микропроцессоров, так как названия ранних моделей процессоров Intel заканчивались на число 86 — 8086, 80186, 80286 (i286), 80386 (i386), 80486 (i486). Более поздние модели стали называть именами собственными (например, Pentium), чтобы иметь возможность зарегистрировать их как торговую марку. Другое название для архитектуры этого типа — IA (англ.) (Intel Architecture) или же IA-32.

Архитектура х86 впервые была применена в процессоре Intel 8086, выпущенном в 1975 году как замена Intel 8085. Однако, он был несовместим с предшественником ни программно, ни аппаратно ­– позднее, для более быстрого перехода на новую архитектуру, был выпущен процессор 8088, имевший ту же ширину шины данных, что и 8085 и совместимый со старыми материнскими платами. Настоящим прорывом стал вышедший в 1985 году Intel 80386, поддерживавший новые 32-битные инструкции. А в 1999-2003 годах корпорацией AMD было разработано новое расширение инструкций – уже до 64х бит, названное x86-64.

x86 — это CISC-архитектура. Доступ к памяти происходит по «словам». «Слова» размещаются по принципу little-endian. Современные процессоры включают в себя декодеры команд x86 для преобразования их в упрощённый внутренний формат с последующим их выполнением, тем самым они являются RISC и CISC одновременно.

У оригинальных Intel 8086 и 8088 есть четырнадцать 16-разрядных регистров. Четыре из них (AX, BX, CX, DX) являются регистрами общего назначения (хотя у каждого может быть дополнительное назначение). Четыре сегментных регистра (CS, DS, SS и ES) используются для формирования адресов в памяти. Существует два регистра-указателя: SP, который указывает на основание стека, и BP, который используется, чтобы указать на некоторое другое место в стеке или памяти (смещение). Два регистра (SI и DI) для индексации массивов. Регистр FLAGS содержит т.н. «флаги», такие как признак переноса, флаг переполнения и нулевой флаг. Наконец, указатель машинной команды (IP) указывает на следующую машинную команду, которая будет выбрана в памяти и затем выполнена.

Процессоры x86 также включают различные особенные/разные регистры, такие как регистры контроля (CR0…4), регистры отладки (DR0…3, плюс 6 и 7), регистры проверки (TR4…7), дескрипторные регистры (GDTR, LDTR, IDTR), и регистр задач (TR).

Процессоры х86 имеют 3 режима работы: реальный, защищённый режим и 64х-битный режим.

Реальный режим – классический режим, использованный в ранних IBM PC. Позволяет адресовать 1 мегабайт памяти и не имеет встроенных средств для защиты памяти и переключения задач, что, впрочем, не мешает реализовать программную многозадачность.

Защищенный режим – 32-разрядная архитектура позволяет адресовать до 4 Гбайт ОЗУ. В 32-битном режиме появилось понятие линейного адресного пространства. Теперь каждая задача может иметь отдельное адресное пространство и использовать до 4 Гбайт памяти независимо от количества установленной физической памяти (ОЗУ). В более поздних 32-разрядных процессорах появилось PAE (Physical Address Extension) — расширение адресов физической памяти до 36 бит (возможность адресации 64 Гбайт ОЗУ). Это изменение не затронуло разрядности задач — они остались 32-битными (каждая задача может иметь отдельное адресное пространство и использовать до 4 Гбайт памяти независимо от количества установленной ОЗУ).

64х-битный режим – к началу 2000-х годов стало очевидно, что 32-битное адресное пространство архитектуры x86 ограничивает производительность приложений, работающих с большими объёмами данных. 32-разрядное адресное пространство позволяет процессору осуществлять непосредственную адресацию лишь 4 Гб данных, этого может оказаться недостаточным для некоторых приложений, связанных, например, с обработкой видео или обслуживанием баз данных. Компания AMD предложила решение проблемы увеличения разрядности процессора. Вместо того, чтобы изобретать совершенно новую систему команд, было предложено ввести 64-разрядное расширение к уже существующей 32-разрядной архитектуре x86. Первоначально новая архитектура называлась x86-64, позже она была переименована в AMD64. Успех процессоров, использующих технологию AMD64, наряду с вялым интересом к собственной архитектуре IA-64, побудили Intel лицензировать набор инструкций AMD64. При этом был добавлен ряд специфических инструкций, не присутствовавших в изначальном наборе AMD64. Новая версия архитектуры получила название EM64T.

Расширениями архитектуры х86 являются MMX, SSE и 3DNow!

MMX – дополнительный «мультимедийный» (англ. Multi-Media eXtensions) набор инструкций, выполняющих по несколько характерных для процессов кодирования/декодирования потоковых аудио/видеоданных действий за одну машинную инструкцию. Впервые появился в процессорах Pentium MMX. Обеспечивает только целочисленные вычисления.

SSE (англ. Streaming SIMD Extensions – потоковое SIMD-расширение) – это SIMD набор инструкций, разработанный Intel и впервые представленный в процессорах серии Pentium III. Поддерживает вычисления с плавающей точкой.

3DNow! – набор инструкций для потоковой обработки вещественных чисел одинарной точности. Поддерживается процессорами AMD. Процессорами Intel не поддерживается. Инструкции 3DNow! используют регистры MMX – 3DNow! являются как бы «преемниками» MMX, их эволюцией.


The Intel architecture is usually called x86. The generic term x86 refers to the most commercially successful instruction set architecture in the history of personal computing. It derived from the model numbers, ending in "86", of the first few processor generations backward compatible with the original Intel 8086. Since then, many additions and extensions have been added to the x86 instruction set (such as MMX, SSE, 3DNow!, x86-64), almost consistently with full backwards compatibility. The architecture has been implemented in processors from Intel, Cyrix, AMD, VIA, and many others.

As the x86 term became common after the introduction of the 80386 in 1985, it usually implies a binary compatibility with the 32-bit instruction set of the 80386. This may sometimes be emphasized as x86-32 to distinguish it either from the original 16-bit x86-16 or from the newer 64-bit x86-64 (also called x64). Although most x86 processors used in new personal computers and servers have 64-bit capabilities, to avoid compatibility problems with older computers or systems, the term x86-64 is often used to denote 64-bit software, with the term x86 implying only 32-bit.

The latest x86 processors have 27 32-bit registers (plus 8 64-bit registers in CPU that supports x86-64). They have 3 operating modes: real, protected and 64-bit mode. In 32-bit protected mode they can address up to 1 Gb of system memory per task, and with PAE – up to 4 Gb per task.

Today, the x86 architecture is usual among desktop and notebook computers, as well as a growing majority among servers and workstations. A large amount of software supports the platform, including OSs such as MS-DOS, Windows, GNU/Linux, BSD, Solaris, and Mac OS X. The architecture is relatively uncommon in embedded systems and low-cost niches such as appliances and toys lack any significant x86 presence.

Contrary to some popular belief, x86 is not synonymous with IBM PC compatibility as this also implies a multitude of other hardware, albeit with some of it standardized.


  • Instruction set (набор инструкций) – set of CPU commands to manipulate data and execute some often used operations.

  • Data bus (шина данных) – physically – set of circuits to transfer information as electrical signal; in general – this set of circuits and set of commands to manipulate information, control its loss, control its destination, etc.

  • DRAM, Dynamic Random Access Memory (динамическая память с произвольным доступом) – a type of random access memory that stores each bit of data in a separate capacitor within an integrated circuit. Since real capacitors leak charge, the information eventually fades unless the capacitor charge is refreshed periodically; it is volatile memory, since it loses its data when the power supply is removed.

  • Microarchitecture (микроархитектура) – more narrow concept than architecture – it means how CPU will translate and process architecture-based commands that are given it by OS.

  • Register (регистр) – a small amount of storage available on the CPU whose contents can be accessed more quickly than storage available elsewhere.

  • SIMD, “Single Instruction, Multiple Data” (Одна инструкция, Множество данных) – a technique employed to achieve data level parallelism. For example, MMX, SSE and 3DNow!


    1. How the Intel architecture is usually called?

    2. What extensions of x86 processors can you name?

    3. When did term “x86” become common?

    4. What is the first x86 processor?

    5. How many registers have the latest x86 processors?

    6. How much memory can be addressed by x86 processor per task?

    7. When was first 32-bit x86 processor introduced?

    8. What operation systems support x86 processors?

    9. Where are x86 processors not present?

Смотрите также:
Реферат по английскому языку. The Intel architecture студент группы 07-р-2 Галанин Иван Проверил
1 стр.
Реферат Предмет: География Тема: Италия студент группы 20м Хилиманюк П. А. Проверил
6 стр.
Реферат на тему: студент группы сп 00 Д1 Иванов Сергей Тихонович Проверил: Егоров С. Н
1 стр.
Реферат Экологическая обстановка Донбасса студент группы мт-121 Косенко Р. В. Проверил: Деменко А. В
3 стр.
Реферат по курсу: История отечества Тема: Исторический портрет русского полководца: П. И. Багратион студент группы РФ 00 2 Азизов М. А
1 стр.
Программа вступительных испытаний по английскому языку по направлениям подготовки: 035700. 62 Лингвистика
1 стр.
Рабочая программа по английскому языку моу «Гимназия №12» с татарским языком обучения учителя английского языка
3 стр.
Книга для чтения Негневицкая Е. И. Пробное учебное пособие по английскому языку Кузнецова Т. И. Тематическое и поурочное планирование по английскому языку Хаткевич О. А. В помощь учителю английского языка
1 стр.
Реферат: Особенности эмо на энергетических и промышленных объектах студент гр. Эд-43 Мамаев А. Ю. Проверил
1 стр.
Тематическое планирование по английскому языку к умк «Spotlight 9»
5 стр.
[ Кафедра ] Контрольная работа Предмет: Финансовый менеджмент тема: Вариант 4 Студент [Курс ] курса Группы [№ группы ] Проверил: [фио преподавателя ]
1 стр.
Реферат на тему: " аристотель основатель науки Логики" Студент группы 226 Родин Д. И
1 стр.